1. Field
This disclosure relates generally to the field of analog-to-digital converters, and more specifically, to a pipelined analog-to-digital converter that provides a high sample rate while also having decreased power usage over other types of pipelined analog-to-digital converters.
2. Related Art
Applications such as digital video, wireless communications, and sensor signal interpretation often require low power and high speed analog-to-digital signal conversion. Pipelined analog-to-digital converters (ADCs) offer a combination of high throughput and small area. Pipelined ADCs are commonly used for medium to high resolution applications that can tolerate latency associated with the pipeline as signals are processed through each pipeline stage.
In order to keep pace with increasing system clock and data rates, a technique of time interleaving an array of parallel ADCs to achieve high throughput has been applied in a variety of applications, including digital storage oscilloscopes. Traditionally, in such parallel ADC pipelines, the input voltage is converted to a digital code at a desired sample rate, while the internal circuitry of each ADC stage processes samples of the input stream at a slower internal frequency (e.g., one-half the sample frequency for two parallel pipelines). This relaxes constraints on the internal circuitry of the ADC pipelined stages.
A drawback of such parallel signal processing is that the parallel pipeline channels sample the input signal on a number of clock edges equal to the number of parallel pipes. In addition there can also be mismatches (gain errors), offsets, and timing inaccuracies between the channels. This can have an effect of generating significant spurs in frequency response of the overall ADC system. Techniques that have been used to correct for these output issues (e.g., calibration and auto-zeroing of the circuits, or design of the clock circuitry) have shown deficiencies at higher input frequencies, or require use of circuitry that consumes power and space without contributing to the conversion process.
It is therefore desirable to have an ADC that provide the high speed and low power benefits of parallel pipelined ADCs, while at the same time avoiding the frequency response problems exhibited by traditional time-interleaved pipeline ADC methods.
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